DRMI=MASTER_TRANSMITTER_D, TFE=TX_FIFO_CONTAINS_VAL, RFE=RX_FIFO_CONTAINS_DAT, TFF=TX_FIFO_IS_NOT_FULL_, RFF=RX_FIFO_IS_NOT_FULL, DRSI=SLAVE_TRANSMITTER_DO, NAI=LAST_TRANSMISSION_RE, AFI=NO_ARBITRATION_FAILU, TDI=TRANSACTION_HAS_NOT_
I2C Status
| TDI | Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions. 0 (TRANSACTION_HAS_NOT_): Transaction has not completed. 1 (TRANSACTION_COMPLETE): Transaction completed. |
| AFI | Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register. 0 (NO_ARBITRATION_FAILU): No arbitration failure on last transmission. 1 (ARBITRATION_FAILURE_): Arbitration failure occurred on last transmission. |
| NAI | No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO. 0 (LAST_TRANSMISSION_RE): Last transmission received an acknowledge. 1 (LAST_TRANSMISSION_DI): Last transmission did not receive an acknowledge. |
| DRMI | Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn’t followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO. 0 (MASTER_TRANSMITTER_D): Master transmitter does not need data. 1 (MASTER_TRANSMITTER_N): Master transmitter needs data. |
| DRSI | Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn’t followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO. 0 (SLAVE_TRANSMITTER_DO): Slave transmitter does not need data. 1 (SLAVE_TRANSMITTER_NE): Slave transmitter needs data. |
| Active | Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen… |
| SCL | The current value of the SCL signal. |
| SDA | The current value of the SDA signal. |
| RFF | Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it. 0 (RX_FIFO_IS_NOT_FULL): RX FIFO is not full 1 (RX_FIFO_IS_FULL): RX FIFO is full |
| RFE | Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data. 0 (RX_FIFO_CONTAINS_DAT): RX FIFO contains data. 1 (RX_FIFO_IS_EMPTY): RX FIFO is empty |
| TFF | Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full. 0 (TX_FIFO_IS_NOT_FULL_): TX FIFO is not full. 1 (TX_FIFO_IS_FULL): TX FIFO is full |
| TFE | Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data. 0 (TX_FIFO_CONTAINS_VAL): TX FIFO contains valid data. 1 (TX_FIFO_IS_EMPTY): TX FIFO is empty |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |